Saltar navegación principal
Norma
IEC 63011-1:2018

IEC 63011-1:2018

Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology

Circuits intégrés - Circuits intégrés tridimensionnels - Partie 1 : Terminologie

Fecha:
2018-11-28 /Vigente
Resumen (inglés):
IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.
Resumen (francés):

Comprar en AENOR

Esta norma está disponible en:

Formato digital

Bilingue